Characteristics of a 'HARP' signal processor with analog memory operated with segmented silicon detectors

For future particle experiments, the detector systems will have a large number of detecting elements, and these will provide raw data at ∼ 50 MHz rates. As an example, the silicon outer tracker (SIT) for the ATLAS detector may consist of 5 planes of silicon strip and pad detectors with 390,000 independent channels per plane. The signal processing electronics must comply with the strong limitation on electrical power and cooling in the central barrel. A 32 channel analog VLSI detector readout chip (HARP32) with an input charge preamplifier, a 64-cell current integrating analog memory in each channel and a common analog multiplexer, has been used in a test beam with segmented silicon detectors. The device was operated at the LHC clock speed of 66 MHz. The different pedestal variations seen at the output are analyzed: the input noise σn amounts to 2.8mV r.m.s., the pedestal non-uniformity in channel σped to 1.2mV r.m.s., the channel to channel pedestal variation σch to 4.0mV r.m.s., and an output baseline shift σobs of 3.5mV r.m.s. has been observed