Strain engineering in SOI-type materials for future technologies

Silicon-on-insulator (SOI) is today the substrate of choice for several applications, including high performance and low power ICs. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement to meet the performance needs of the 65 nm technology nodes and beyond. One possible option is to increase transistor channel mobility through local strain engineering via stressors like nitride layers or epitaxial SiGe source/drain pockets. This is the so-called 'local strain' or 'process-induced strain' approach. Another solution is to induce a MOSFET mobility increase via substrate engineering, which presents the advantage of being independent of transistor geometry. If necessary, the two approaches can be combined. The attractiveness of wafer level-based solutions is largely due to their compatibility with standard CMOS integration processes and architectures. Among the different substrate level options investigated by the industry, we will focus here on strained Si layers on insulator. Different wafer manufacturing techniques will be considered, and the potential of wafer bonding and layer transfer techniques will be highlighted