A hardened technology on SOI for analog devices

This paper is dedicated to the presentation of a hardened and mixed analog-digital technology under development. This technology now includes a PJFET with a quite good hardness, CMOS transistors with a potential multi-Megarad hardness and first tests of bipolar transistors with a not yet optimized structure (structure of the JFET). All the results achieved so far, together with the optimizations under way will lead to an analog technology with a digital capability and a high level of hardness (neutron fluence, cumulated dose, immunity to upsets) to address the needs of military applications and electronics for the elementary particles physics detectors of the next generation colliders