Silicon defects characterization for low temperature ion implantation and RTA process

In the last years a lot of effort has been directed in order to reduce silicon defects eventually formed during the ion implantation/anneal sequence used in the fabrication of CMOS devices. In this work we explored the effect of ion implant dose rate and temperature on the formation of silicon defects for high fluence ⁴⁹BF₂ implantations. The considered processes (implantation and annealing) conditions are those typically used to form the source/drain regions of p-channel transistors in the submicron technology node and will be detailed in the document. Characterization of implant damage and extended silicon defects left after anneal has been performed by TEM. Dopant distribution and dopant activation has been investigated by SIMS and SRP analysis. We have verified that implant dose rate and temperature modulate the thickness of the amorphous silicon observed after implant, as well as the concentrations of silicon defects left after anneal. Effect of high dose rate low temperature implantation on product device was also evaluated, showing a reduction of leakage current on p-channel transistors. Experimental set up, results and possible explanation will be reported and discussed in the paper.