[en] The full potential of a semiconductor research and prototyping tool is rarely realized before it is integrated into a fabrication line. Once the equipment is the process flow, its streams can be used to give the facility new capabilities and the extent to which its weaknesses can be overcome can be realistically evaluated. With 0.1-μm alignment and dimensions in mind, the goal of this work was to integrate the FIB into an integrated-circuit processing line, and demonstrate the FIB capabilities by fabricating improved MOS devices. Four MOS test vehicles were chosen to demonstrate the features of the FIB, in two distinct integrated circuit processing lines. Each of the four experiments demonstrated different capabilities of the FIB. The high-gain MOSFET is a 1.6-μm long with a highly localized (0.1 μm) FIB B implant in the channel. The channel implant controls the device threshold and reduces the effective channel length. A technique for combining optical and FIB lithography on the same layer is described. By merging the two lithographic techniques, large features can be generated optically and small features can be generated with the FIB, significantly reducing FIB writing time

[en] This paper describes a 3-μm CMOS timing sampler which is a test circuit designed into the JPL CRRES chip to be flown on the combined Release and Radiation Effects Satellie (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches and decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 nanoseconds, with a resolution of 100 picoseconds. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET-threshold voltage shifts and effective nodal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-volt threshold shift, the pair-delay increased from its preradiation value by 360 picoseconds for a rising step input and decreased by 190 picoseconds for a falling step input

[en] This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ₀) and the low-field mean free path (λ₀), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ₀ is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ₀ is nearly a constant, and λ₀ can be used as the 'entry criterion' to determine whether the device begins to operate under quasi-ballistic transport to some extent. (semiconductor devices)

[en] During investigations of a CRYO-CMOS technology suitable for very low temperatures, the authors acquired substantial experience concerning cryogenic measurement techniques. This paper describes their test assembly, which enables computer-aided acquisition of measurement data in the temperature range between 2 and 300 Κ

[en] For compact modeling of the organic field-effect transistor above-threshold drain current, we suggest using an approach that was recently proposed for the improved compact MOSFET model with the correct accounting of the nonzero output conductance in the saturation regime. This approach ensures a monotonic decrease of transistor output conductance from its maximum value in the linear regime to the minimum value in the saturation regime. (paper)

[en] In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET. (paper)

[en] Scaling MOSFETs becomes more and more difficult. The tunnelling-FET is a possible successor of today's MOSFET with better scaling possibilities. Two different device structures, a vertical and a planar version of a tunnelling-FET are presented and evaluated

[en] A reproducible and controllable induction adder was developed using solid-state switching devices and Finemet cores for scaled beam compression experiments. A gate controlled MOSFET circuit was developed for the controllable voltage driver. The MOSFET circuit drove the induction adder at low magnetization levels of the cores which enabled us to form reproducible modulation voltages with jitter less than 0.3 ns. Preliminary beam compression experiments indicated that the induction adder can improve the reproducibility of modulation voltages and advance the beam physics experiments.

[en] This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n^- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication. (semiconductor devices)

[en] A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET. A 0.12 μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method. The trapped charge distribution with a narrow peak can be precisely characterized with this method, which shows good consistency with the measured threshold voltage. (semiconductor devices)