Results 1 - 10 of 7991
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[en] The price drop in the large scale integrated semiconductor elements now permits the use of the 2v3-principle on the microcomputer level. In a diploma thesis, the advantages and disadvantages of such an error-tolerant arrangement has been looked into and discussed using a model. A report is given on the hardware costs and the necessary software expenditure. Further improvement possibilities are also shown. (orig.)
[de]Der Preisverfall der hochintegrierten Halbleiterbauelemente erlaubt nunmehr die Anwendung des 2v3-Prinzips auf Mikrocomputer-Ebene. Im Rahmen einer Diplomarbeit wurden anhand eines Modells die Vor- und Nachteile einer derartigen fehlertoleranten Anordnung untersucht und diskutiert. Ueber Hardwarekosten und den erforderlichen Softwareaufwand wird berichtet. Weitere Verbesserungsmoeglichkeiten werden aufgezeigt. (orig.)
[en] The main features of Control Panel for CAMAC Crate Controller CMC 8080 are described. The control panel can be directly connected with CRATE CONTROLLER's front panel connector with a 50 lines cable without any changes in CMC 8080 system circuits. (author)
[en] The universal tester with a microprocessor which uses a INTEL 8085A for CPU of the tester is described. This instrument contains the switch-mode output ports, the programming I/O ports, CAMAC special interface, DAC output port, ADC input port and display of relative status and data. The amplitude measuring channel and the time measuring channel are made up from mentioned ports. Having a single-step and a break-point control circuits the tester is available to test and measure the nuclear electronics modules
[en] The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.)
[de]Ziel des urspruenglich fuer 3 Jahre geplanten Vorhabens war die Entwicklung moderner System- und Schaltungskonzepte fuer VLSI-Prozessoren mit 32 Bit Verarbeitungsbreite. Das im ersten Jahr erzielte Ergebnis ist die Konzeption eines Universalprozessors. Dieser Prozessor ist nicht nur logisch, sondern auch von der Chip-Organisation her in vier Funktionseinheiten strukturiert: Ein mikroprogrammiierbares Leitwerk, ein Rechenwerk in Slice-Technik, ein vollassoziativer Pufferspeicher und ein Ein/Ausgabewerk. Fuer die arithmetisch-logische Einheit des Rechenwerkes wurden Schaltungen in PLA- und Slice-Technik realisiert. Bezueglich Regularitaet, Flaechenbedarf und erzielbarer Leistungsdaten ist die Slice-Technik hier vorzuziehen. Die Entwuerfe beruecksichtigen selbsttestende Schaltungen. (orig.)
[en] A multiprocessor system designed for rapid analysis of data is described and its performance is evaluated in a complex histogramming application. The system consists of several general purpose processors coupled to the Multibus with a shared memory that is used for intercommunication between the processors and a host VAX-11/780 computer. (orig.)
[en] The MC68020 is a 32-bit microprocessor object code compatible with the earlier MC68000 and MC68010. In this paper we describe its architecture and two coprocessors: the MC68851 paged memory management unit and the MC68882 floating point coprocessor. Between its most important characteristics we can point up: addressing mode extensions for enhanced support of high level languages, an on-chip instruction cache and full support of virtual memory. (Author)
[en] In this paper we describe the main topics about the architecture of the best known 32-bit CISC microprocessors; i80386, MC68000 family, NS32000 series and Z80000. We focus on the high level languages support, operating system design facilities, memory management, techniques to speed up the overall performance and program debugging facilities. (Author)
[en] Plasma waves are important observational targets for scientific satellite missions to investigate electromagnetic phenomena that occur in space. For future scientific missions, reduction in the resource requirements of plasma wave receivers without loss of performance is important. This paper introduces a miniaturized on-board instrument for the observation of plasma waves using analogue application-specific integrated circuit (ASIC) techniques. The developed ASIC functions as a system chip to filter and amplify signals detected by plasma wave sensors. Miniaturization of the analogue circuit using the ASIC leads to the realization of a tiny plasma wave receiver. The overall size of the developed plasma wave receiver circuit board is less than 1/20 that of a conventional receiver used in previous scientific missions. The power consumptions of the system chip and the plasma wave receiver are 165 and 525 mW, respectively. (paper)
[en] We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines.
[en] In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.