No abstract available

[en] This invention concerns a system for biasing a differential amplifier. It particularly applies to the integrated differential amplifiers designed with MOS field effect transistors. Variations in the technological parameters may well cause the amplifying transistors to work outside their usual operational area, in other words outside the linear part of the transfer characteristic. To ensure that these transistors function correctly, it is necessary that the value of the voltage difference at the output be equally null. To do this and to centre on the so called 'rest' point of the amplifier transfer charateristic, the condition will be set that the output potentials of each amplifier transistor should have a zero value or a constant value as sum. With this in view, the bias on the source (generally a transistor powered by its grid bias voltage) supplying current to the two amplifying transistors fitted in parallel, is permanently adjusted in a suitable manner

[en] The main technological steps applied to P channel MOSFET's on SOS are recalled. A large-signal model derived from a physical analysis is presented. Gate-source and gate-drain capacitors have been linearized versus drain voltage. Due to low injection, the only diffusion capacitance of the source-substrate forward biased diode, and the depletion capacitance of the drain-substrate reverse biased diode were taken into account. Some typical parameters measured on SOS and bulk devices are given

[en] The reasons for trying to decrease MOSFET device dimensions are briefly recalled. Theoretical and experimental results obtained for micron MOSFETS are then presented

No abstract available

[en] Doping of the source and drain of the MOS field effect transistor (Si substrate with oxide layer) follows by P ions. The gate electrode is used as an implantation ion mask. Because it is not possible to prevent doping in the shaded range of the mask, the mask exhibits a lateral expansion, that keeps clear smaller doping areas as are desired. After the ion implantation, first the implantation mask is eroded by means of surface pulverization, plasma etching or a bent ion beam, at their edges, in a way that the desired sizes of the source and drain areas are conserved. (DG)

No abstract available

No abstract available

[en] A comprehensive study of band structure effect on the quantum transport of nanoscale In_0.53Ga_0.47As Schottky MOSFET for the implementation of III–V MOSFET with low source/drain series resistance is presented. Rigorous treatment of the full band structure in ultra-thin body MOSFET is employed using sp³d⁵s^* tight-binding approach. Strong transverse confinement increases the energy of subbands and, indeed, the effective Schottky barrier height. Due to enhanced Schottky barriers and at low drain voltages, a double barrier gate modulated potential well is created along the channel that results in source-to-drain confinement of states. As tunnelling is the main current component in this device, longitudinal confinement induces drain current oscillation at low temperatures. Important factors that may affect current oscillation are demonstrated. Current oscillation that alters the normal performance of the device is investigated in nanowire Schottky MOSFET, as well. Additional quantum confinement in nanowire Schottky MOSFET provides higher effective Schottky barrier height than the double gate structure. Accordingly, the drain current oscillation is more apparent in nanowire Schottky MOSFET than in the double gate device and is gradually smoothed out as the gate length shrinks down in ultra-scaled structure. Effect of diffusive scattering on the quantum transport of the device is investigated, too. What is prominent in our result is that the drain current oscillations degrade as the channel mobility is decreased. The results in this paper are paving a way to elucidate the feasibility of this device in the nanoscale regime. (paper)

[en] Scaling MOSFETs becomes more and more difficult. The tunnelling-FET is a possible successor of today's MOSFET with better scaling possibilities. Two different device structures, a vertical and a planar version of a tunnelling-FET are presented and evaluated