Filters
Results 1 - 10 of 2849
Results 1 - 10 of 2849.
Search took: 0.041 seconds
Sort by: date | relevance |
AbstractAbstract
No abstract available
Source
International conference on multiply-charged heavy ion sources and accelerating systems; Gatlinburg, Tenn; 25 Oct 1971
Record Type
Journal Article
Literature Type
Conference
Journal
IEEE (Inst. Electr. Electron. Eng.) Trans. Nucl. Sci; v. NS-19(2); p. 321-326
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
Barbier, Daniel; Ittel, J.M.; Poujois, Robert
CEA, 75 - Paris (France)1975
CEA, 75 - Paris (France)1975
AbstractAbstract
[en] This invention concerns a system for biasing a differential amplifier. It particularly applies to the integrated differential amplifiers designed with MOS field effect transistors. Variations in the technological parameters may well cause the amplifying transistors to work outside their usual operational area, in other words outside the linear part of the transfer characteristic. To ensure that these transistors function correctly, it is necessary that the value of the voltage difference at the output be equally null. To do this and to centre on the so called 'rest' point of the amplifier transfer charateristic, the condition will be set that the output potentials of each amplifier transistor should have a zero value or a constant value as sum. With this in view, the bias on the source (generally a transistor powered by its grid bias voltage) supplying current to the two amplifying transistors fitted in parallel, is permanently adjusted in a suitable manner
[fr]
La presente invention concerne un dispositif de polarisation d'un amplificateur differentiel. Elle s'applique notamment aux amplificateurs differentiels integres realises avec des transistors a effet de champ du type MOS; des variations des parametres technologiques risquent de faire travailler les transistors amplificateurs hors de leur zone normale de fonctionnement, c'est-a-dire hors de la partie lineaire de la caracteristique de transfert. Pour assurer un bon fonctionnement de ces transistors, il est necessaire que, pour une difference de tension a l'entree nulle, la valeur de la difference de tension en sortie soit egalement nulle. Pour ce faire et se centrer sur le point dit point de 'repos' de la caracteristique de transfet de l'amplificateur, on imposera la condition que les potentiels de sortie sur chaque transistor amplificateur, aient pour somme la valeur zero ou une valeur constante. Dans ce but, on adapte en permanence de maniere convenable la tension de polarisation sur la source (generalement un transistor attaque par la tension de polarisation sur sa grille) alimentant en courant les deux transistors d'amplification disposes en paralleleOriginal Title
Dispositif de polarisation d'un amplificateur differentiel
Source
15 Jul 1975; 10 p; FR PATENT DOCUMENT 2318533/A/; Available from Institut National de la Propriete Industrielle, Paris (France)
Record Type
Patent
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
Merckel, G.; Gris, Y.
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1976
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1976
AbstractAbstract
[en] The main technological steps applied to P channel MOSFET's on SOS are recalled. A large-signal model derived from a physical analysis is presented. Gate-source and gate-drain capacitors have been linearized versus drain voltage. Due to low injection, the only diffusion capacitance of the source-substrate forward biased diode, and the depletion capacitance of the drain-substrate reverse biased diode were taken into account. Some typical parameters measured on SOS and bulk devices are given
[fr]
On rappelle les principales etapes de la technologie appliquee aux MOSFETS a canal P sur SOS. Un modele a grand signal tire d'une analyse physique est presente. Les condensateurs de la porte-source et porte-drain ont ete linearises en fonction de la tension de drainage. En raison de la faible injection, seules la capacitance de diffusion du substrat-source de la diode a polarisation directe, et la capacitance d'appauvrissement du substrat drain de la diode a polarisation inverse ont ete prises en compte. Quelques parametres caracteristiques mesures pour les dispositifs SOS et les dispositifs pris dans la masse sont donnesSource
25 Mar 1976; 14 p; 5. European solid state device research conference; Grenoble, France; 8 Sep 1973; CEA-LETI-MEA--1145
Record Type
Report
Literature Type
Conference
Report Number
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
Gautier, J.; Borel, J.; Merckel, G.
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1975
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1975
AbstractAbstract
[en] The reasons for trying to decrease MOSFET device dimensions are briefly recalled. Theoretical and experimental results obtained for micron MOSFETS are then presented
[fr]
On rappelle brievement les raisons pour lesquelles on essaye de diminuer les dimensions des dispositifs MOSFET. On presente ensuite les resultats theoriques et experimentaux obtenus pour les MOSFETS a dimension de l'ordre du micronSource
03 Feb 1975; 17 p; 4. European solid state device research conference (ESSDERC 74); Nottingham, UK; 16 Sep 1974; CEA-LETI-MEA--1070
Record Type
Report
Literature Type
Conference
Report Number
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
AbstractAbstract
No abstract available
Original Title
MOS-FET als Sensoren fuer bioelektrische Vorgaenge
Source
44. physiscists meeting. Joint meeting with the Fachgremien Atomphysik und Massenspektroskopie, Fachdidaktik der Physik, Duenne Schichten, Geschichte der Physik, Kurzzeitphysik, Molekuelphysik, Oberflaechenphysik, Plasma- und Gasentladungsphysik, Quantenoptik; Bielefeld, Germany, F.R; 3 - 7 Mar 1980; Short communication only.
Record Type
Journal Article
Literature Type
Conference
Journal
Verhandlungen der Deutschen Physikalischen Gesellschaft; (no.5); p. 625
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
Krimmel, E.F.
Siemens A.G., Berlin (Germany, F.R.); Siemens A.G., Muenchen (Germany, F.R.); Deutsches Patentamt, Muenchen (Germany, F.R.)1978
Siemens A.G., Berlin (Germany, F.R.); Siemens A.G., Muenchen (Germany, F.R.); Deutsches Patentamt, Muenchen (Germany, F.R.)1978
AbstractAbstract
[en] Doping of the source and drain of the MOS field effect transistor (Si substrate with oxide layer) follows by P ions. The gate electrode is used as an implantation ion mask. Because it is not possible to prevent doping in the shaded range of the mask, the mask exhibits a lateral expansion, that keeps clear smaller doping areas as are desired. After the ion implantation, first the implantation mask is eroded by means of surface pulverization, plasma etching or a bent ion beam, at their edges, in a way that the desired sizes of the source and drain areas are conserved. (DG)
[de]
Die Dotierung der Source- und Drain-Gebiete des MOS-Feldeffekttransistors (Si-Substrat mit Oxidschicht) erfolgt mit P-Ionen. Als Implantationsmaske wird die Gate-Elektrode verwendet. Da hierbei eine Dotierung im Schattenbereich der Maske nicht zu verhindern ist, weist diese eine laterale Ausdehnung auf, die kleinere Dotierungsgebiete als gewuenscht freilaesst. Nach der Ionenimplantation wird dann erst die Implantationsmaske mittels Oberflaechenzerstaeubung, Plasma-Aetzen oder geneigtem Ionenstrahl an ihren Raendern derart abgetragen, dass die gewuenschten Abmessungen der Source- und Drain-Gebiete erhalten werden. (DG)Original Title
Verfahren zur selbstjustierenden Herstellung dotierter Gebiete in einem Halbleitersubstrat mittels Ionenimplantation; Siemens
Secondary Subject
Source
14 Sep 1978; 8 p; DE PATENT DOCUMENT 2710266/A/
Record Type
Patent
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
AbstractAbstract
No abstract available
Source
7 figs.; 29 refs.
Record Type
Journal Article
Literature Type
Bibliography
Journal
Zeitschrift fuer Angewandte Physik; v. 32(4); p. 280-286
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
Suat, J.P.; Ducollet, B.; Borel, J.
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1974
CEA Centre d'Etudes Nucleaires de Grenoble, 38 (France). Lab. d'Electronique et de Technologie de l'Informatique1974
AbstractAbstract
No abstract available
Source
17 Oct 1974; 22 p; 4. European solid state device research conference (ESSDERC 74); Nottingham, UK; 16 Sep 1974; CEA-LETI-ME--1046
Record Type
Report
Literature Type
Conference
Report Number
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
AbstractAbstract
[en] Scaling MOSFETs becomes more and more difficult. The tunnelling-FET is a possible successor of today's MOSFET with better scaling possibilities. Two different device structures, a vertical and a planar version of a tunnelling-FET are presented and evaluated
Primary Subject
Source
2. conference on microelectronics, microsystems and nanotechnology; Athens (Greece); 14-17 Nov 2004; Available online at http://stacks.iop.org/1742-6596/10/15/jpconf5_10_004.pdf or at the Web site for the Journal of Physics. Conference Series (Online) (ISSN 1742-6596) http://www.iop.org/; Country of input: International Atomic Energy Agency (IAEA)
Record Type
Journal Article
Literature Type
Conference
Journal
Journal of Physics. Conference Series (Online); ISSN 1742-6596;
; v. 10(1); p. 15-18

Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
External URLExternal URL
AbstractAbstract
[en] A reproducible and controllable induction adder was developed using solid-state switching devices and Finemet cores for scaled beam compression experiments. A gate controlled MOSFET circuit was developed for the controllable voltage driver. The MOSFET circuit drove the induction adder at low magnetization levels of the cores which enabled us to form reproducible modulation voltages with jitter less than 0.3 ns. Preliminary beam compression experiments indicated that the induction adder can improve the reproducibility of modulation voltages and advance the beam physics experiments.
Primary Subject
Secondary Subject
Source
(c) 2016 Author(s); Country of input: International Atomic Energy Agency (IAEA)
Record Type
Journal Article
Journal
Country of publication
Reference NumberReference Number
INIS VolumeINIS Volume
INIS IssueINIS Issue
External URLExternal URL
1 | 2 | 3 | Next |