[en] The original MMF compensation method allows the magnetic properties of single sheets and strips to be measured in the same way as the closed specimen properties. The accuracy of the method is limited due to the finite gain of the feedback loop fulfilling the condition of its stability. Digitalisation of the compensation loop appropriate processing of the error signal can rapidly improve the accuracy. The basic ideas of this new approach and the experimental results are described in this paper

[en] The paper describes a new method for high resolution nuclear timing spectroscopy system using tracking ADCs and free running ramp to give the timing resolution of few ps over wide dynamic range of time interval extending up to few µs. The method makes use of tracking ADCs with 16 bit resolution with low conversion time of nearly 1 µs along with a free running ramp which is given as input to the two ADCs. Both the ADCs and ramp are designed to track their characteristics in order to neutralize the errors due to drift in their characteristics and hence complex system of spectrum stabilization is not required. ADC1 digitizes ramp input at the arrival of START pulse and ADC2 digitizes ramp input at the arrival of STOP pulse. The difference between digital codes of these ADCs is a measure of time interval between START and STOP pulses. New system doesn’t require delay and hence biased amplifier. System has dead time of 1 µs and spectrum stabilization is easy. (author)

[en] We have been developing a third-order sinc decimation filter in order to realize an oversampling sigma delta A/D converter with a second-order modulator. The sinc filter is formed from a multistage decimation structure, which is suitable for a high-speed operation. A 4-bit destructive readout (DRO) counter, which was an elementary circuit of the sinc filter and was also utilized as a first-order sinc filter with a decimation factor of 8, was designed and its proper operation was confirmed with a dc bias current margin of ±33% from a low-frequency measurement. The 4-bit DRO counter also operated up to the data rate of 4.8 Gbps with a dc bias current margin of ±29% from a high-frequency measurement. The third-order sinc filter with a decimation factor of 2, which was an elementary circuit block of our multistage decimation third-order sinc filter, was designed and its proper operation was confirmed from a low-frequency measurement. The third-order sinc filter with a decimation factor of 2 consisted of a 3-bit shift register, three 2-bit DRO counters and a 4-bit DRO counter, containing 441 junctions, and its power consumption was estimated to be 59 μW. (author)

[en] The MCOR 12 is a 16-channel modular architecture, precision magnet driver, capable of providing bipolar output currents in the range from –12A to +12A. A single, unregulated bulk power supply provides the main DC power for the entire crate. Currently the MCORs have a 1000ppm regulation on the B-field. The MCOR controller card upgrades, existing LCLS-I and future LCLS-II needed, controls for Magnet Corrector Power Supplies. The project shifts the existing functionality of the VME based DAC and SAM and an Allen Bradley PLC into a new slot-0 card residing in the MCOR chassis. Elimination of the VME crate and the PLC will free up rack space to be used in future. The new interface card has a long term stability of 100ppm and monitors ground fault currents and various other interlocks for the MCOR power supplies. The controller can interface to EPICS Channel Access and Fast Feedback system at SLAC using two Gigabit Ethernet ports and has an FPGA based EVR for getting “time stamps” from the Event Generato system at SLAC. The EPICS control system along with embedded diagnostic features will allow for enhanced remote control and monitoring of the power supplies. (author)

[en] New multiple-valued logic applications for designing digital devices are considered. The multiple-valued logic gives more opportunities for realization of digital processing algorithms than traditional binary logic. One can more efficiently solve the problems of binary logic, namely: find alternative ways of calculations, better understand, easier formalize and solve the problems of logical design. Using the multilevel signals for design of multiple-valued memories, arithmetic circuits, Field Programmable Gate Arrays has several potential opportunities for the improvement of circuits, namely: to reduce the difficulties with limitations on the number of connections of an integrated circuit with the external world (pin-out problem) as well as on the quantity of connections inside the circuit; to reduce or eliminate the ripple-through carries which are involved in normal binary addition or subtraction; to reduce a total number of active elements

[en] This book consists of 18 chapters, which deal with introduction of analog and digital, number system, logical function, simplify of logic function, digital logic gate, basic circuit, multiplex and de multiplex, adder-subtractor, encoder and decoder, comparator circuit and check circuit, flip-flop, counter, shift register, monostable multivibrator, DA converter, interface and memory and micro processor. The end has exercises and answers and an index.

[en] This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

[en] Short communication. 1 fig

No abstract available

No abstract available