[en] Applications of new developments in CAMAC during the past year are reviewed and its future is considered in view of related technological developments

[en] This article introduces the interface design of Motorola microcontroller by using the Philips USB interface chip, PDIUSBD12. (authors)

[en] A CAMAC system for a readout from various groups of modules is described. The system is based on a read-only controller and a special LAM grader. According to arriving L signals and their patching in the LAM-grader, signals for the following operations can be generated: a readout in the address scan mode, a block transfer from one address (using the BQL-mode), disabling the readout from some groups of stations and ending the readout. The system is very flexible and may consist of both one and several crates

[en] The I/O Register to FASTBUS Interface (IORFI) is connected to a processor via two 16-bit output registers (OR1,OR2) and two 16-bit output resisters (IR1,IR2). One of the output registers (OR1) is used to specify the interface function which is to be performed when the interface is accessed via the Data-in Register (IR2) or the Data-out Register (OR2). The other input register (IR1) is used to read the direct status of the FASTBUS lines independent of OR1. The changes made to the SLAC design at the University of Illinois are described

[en] In the Nuclear Research Laboratory of the Mongolian State University we have been using the American Perkin Elmer corporation's equipment which is called ''The Atomic Absorption Spectro-Photometer'' (AAS) since 1981. Our task was to connect Perkin Elmer equipment to an IBM/PC compatible computer and to automate the manual operations. We describe a new design of the instruments which allows us to connect the Perkin Elmer equipment ot the IBM PC/XT type computer and consequently to automate its manual operations that are necessary during the measurements of each sample on it. A timing diagram of date signals which should appear on the AAS display and the general principle to operate of the instrument have been reviewed. Finally authors draw your attention to the opto-isolator which is necessary to protect the Perkin Elmer equipment, the IBM/PC/XT computer and the new equipment in case of any accident. In other words the new equipment is connected by the optical isolator link to the computer. 3 figs

[en] Interface equipment for VME bus connection with PRAVETS-16 personal computer is described. Block-diagram the developed equipment which allows to realize data exchange between VME bus and PRAVETS-16 mass memory in on-line and memory access and interrupt priority modes is given

[en] Although FASTBUS has features built into it which allow complex interconnections and multiple Masters, the rules for implementing Slaves are very simple. The first time designer of Slave Modules should not be intimidated by the 200 pages of the FASTBUS document. About 90% of the specification is associated with system implications that do not impact Slave design. This paper will review the basic logic and timing requirements for FASTBUS Slave design. Also, some examples of implementation will be shown. The discussion which follows assumes that mastership of the bus has been gained. Bus arbitration, system interconnection, message routing, etc. are separate topics and will not be discussed here. These topics affect only the design of devices which operate at the system level since FASTBUS Slave modules have been specified to be completely transparent to these system considerations

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No abstract available

[en] The FASTBUS project is an interlaboratory effort to develop a next-generation laboratory standard data bus. The principal design goals are high speed (< 100 ns per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high-energy physics applications. The current status of development is briefly described. 10 figures, 2 tables