No abstract available

No abstract available

[en] This paper is focused on the potential of ion beam lithography for the development, customization and high volume production of sub-0.5-μm devices. (author). 40 refs.; 12 figs

[en] SiOCH ULK films with k-value from 2.5 to 2.1 and porosity from 24 to 40% were etched in CHF₃, CHF₃  +  Ar, CF₄ and CF₄  +  Ar plasmas at  +15…−120 °C with and without bias being applied. It was shown that the presence of Ar in gas mixture can significantly increase the damage of unetched ultra low-k (ULK) material (at sidewalls) due to the removal of  −CH₃ groups from the film by VUV photons. It was also shown that etching and damage of the sidewalls by F atoms can be partially prevented by lowering the temperature of the sample. (paper)

[en] Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth, based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited. The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation. The dynamic characteristics, especially reverse diode characteristics, are equivalent or even superior to foreign counterparts. (semiconductor devices)

[en] A modified CR-39 microfilter with funnel-shaped pore entrances is produced by using a multi-step etching procedure with NaOH and PEWsub(x) solution (PEWsub(x) = 15g KOH + x g C₂H₅OH + (85 - x)g H₂O) as etching agents. The air throughput through this microfilter is measured and compared with the CR-39 microfilter with cylinder-shaped pores and a commercial microfilter (Nuclepore). The experimental data of both CR-39 microfilters show a good agreement with the theoretical values for the air throughout contrary to the Nuclepore microfilter. Furthermore both CR-39 filters have an extremely plane surfaces and no roughness of the pore walls. (author)

[en] The process of trench formation in photo-electrochemical etching of n-type Si (1 0 0) has been studied as dependent on the normalized etching current density j/j_PS and on the line seed period a. Experiments were performed on n-type Si (1 0 0) samples with resistivity ρ = 5 and 15 Ω cm. V-shaped grooves with a period a = 4–13 µm, fabricated on the sample surface, were used as etch seeds. We formulate criteria for macropores merging into trenches and formation of trenches from double-pore rows. The validity of these criteria is confirmed by experimental data. The relationships obtained are based on the tendency of the system to form macropores of a certain diameter d, characteristic of silicon with a given resistivity. We found reasons for the enhanced irregularity of the trench walls and suggest design rules for periodic structures. To obtain a wall array, it is recommended to choose a period that does not differ significantly from the average distance between discrete self-organized macropores, a ≈ ā, and an etching current density within the range πd/4a < j/j_PS < 2d/a

[en] We fabricated p⁺–p–p⁺ junctions in order to properly investigate the electrical conduction across a boron implanted silicon-on-insulator (SOI) nanostructured pattern, like photonic crystals and shallow-etched trenches. By analysis of the I–V measurements, we demonstrate that a depletion region is present and it is induced by the dry etching process of reactive ion etching. This depletion region does not depend on the geometry of the dry-etched nanostructure, but on the doping level of the substrate. (paper)

[en] A novel model was established to investigate the effects of the initial stencil width on stainless steel wet chemical etching. This model was derived to correlate the etching depth with the initial stencil width, etching time and other parameters. Coefficient of determination (COD) was applied to check the fitting accuracy of the model. The model showed good predictive capability for the initial stencil widths ranging from 50 µm to 500 µm. From the derivations of the model, it was found that the etching rate is controlled by the ratio of the area being etched to the area of the stencil opening. Explanations for the variation of the etching depth versus the initial stencil width were also given through a series of mathematical derivations. The limitation of the model and the corresponding reasons were also discussed. This model can be used to predict the etching depth in practical productions when the etching time and the initial stencil width are given

[en] A processing scheme for the manufacturing of an open stencil mask has been set up by application of silicon technology and only one single X-ray lithography step for pattern generation. The mask fabrication is fully adapted to the demands of an ion projection lithography equipment by IMS. It has been proved that this mask technology permits solid structures of a complex geometry with high pattern fidelity. (author). 3 refs.; 7 figs