[en] Published in summary form only

[en] This software package provides a worksheet environment for calculating fire duration and severity based on the method outlined by T.J. Harmathy as presented in his two part paper on compartment fires. This software is intended to aid engineers in designing facilities, ventilation systems, and process systems by allowing combustible loading ''what-ifs'' to be evaluated

No abstract available

[en] The Fontenay numerical code of toroidal discharges is presented. The empirical rules and transport coefficients used in order to fit the experimental data are explained, and a few examples of application are given. A simplified study of the transport equations in the steady state is presented, it gives precise details about the functional form of the transport coefficients and justifies the empirical coefficients used

[en] FISS is a computer code for use in investigating alternative fuel cycle strategies, performing system simulations accounting for the dynamic effects in growing systems. The changes that have been made to the original FISS program reported in AECL-5814 are described

No abstract available

[en] Studsvik Nuclear of Sweden has developed a process code that can simulate internal fuel rod behaviour as a function of a nuclear reactor's power history. The Fuel Rod Performance Simulator (FRPS), has two versions: batch and interactive. Interpin, the batch version, produces results as listings or graphs; the interactive code, Simsim, steps through a power history under user control and instantly evaluates and displays the internal state of the fuel rod at each time step. Both run on minicomputers and PCs using EGA graphics. A third version is used as one of the modules in the Studsvik Compact Simulator. Here the FRPS received the dynamic inputs from the simulator. (author)

[en] FUMILI renovation-2 (FUMILIM) is suggested which has the following advantages: a more convenient and friendly user interface; no restriction to the number of parameters and experimental points; speed advantage when the number of parameters is high enough; a possibility to define analytically an arbitrary number of parameter derivatives. An additional package of the track reconstruction in straw chambers is suggested. The solution speed for the specific tasks was increased many times in comparison with the previous version of FUMILIM. All programs are written using FORTRAN-77

[en] Controllers in safety critical systems such as nuclear power plants often use Function Block Diagrams (FBDs) to design embedded software. The design is implemented using programming languages such as C to compile it into particular target hardware. The implementation must have the same behavior with the design and the behavior should be verified explicitly. For example, the pSET (POSAFE-Q Software Engineering Tool) is a loader software to program POSAFE-Q PLC (Programmable Logic Controller) and is developed as a part of the KNICS (Korea Nuclear Instrumentation and Control System R and D Center) project. It uses FBDs to design software of PLC, and generates ANSI-C code to compile it into specific machine code. To verify the equivalence between the FBDs and ANSI-C code, mathematical proof of code generator or a verification tools such as RETRANS can help guarantee the equivalence. Mathematical proof, however, has a weakness that requires high expenditure and repetitive fulfillment whenever the translator is modified. On the other hand, RETRANS reconstructs the generated source code without consideration of the generator. It has also a weakness that the reconstruction of generated code needs additional analysis This paper introduces verification process of behavioral consistency between design and its implementation of the pSET using the HW-CBMC. The HW-CBMC is a formal verification tool, verifying equivalence between hardware and software description. It requires two inputs for checking equivalence, Verilog for hard-ware and ANSI-C for software. In this approach, FBDs are translated into semantically equivalent Verilog pro-gram, and the HW-CBMC verifies equivalence between the Verilog program and the ANSI-C program which is generated from the FBDs

No abstract available