Results 1 - 10 of 7020
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[en] The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs
[en] Tungsten and other refractory metals can be supplied to a CMOS IC in gate electrodes, metallized or silicided source/drain regions and interconnects. Besides the well-known advantage in reducing intra- and inter-transistor parasitic resistances, hence increasing circuit speed, other advantages in CMOS include improved turn-off characteristics in pMOS FETs, enhanced latch-up immunity and reduced electromigration failure. Meanwhile a new reliability concern has been raised for nMOS FETs with silicided source/drains
[en] Inverse lithography technology (ILT), a promising resolution enhancement technology (RET) used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing methods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the parallel process. The seamless-merging-oriented parallel ILT method proposed in this paper is fast because of the parallel process; and most importantly, convergence enhancement penalty terms (CEPT) introduced in the parallel ILT optimization process take the environment into consideration as well as environmental change through target updating. This method increases the similarity of the overlapped area between guard-bands and work units, makes the merging process approach seamless and hence reduces hot-spots. The experimental results show that seamless-merging-oriented parallel ILT not only accelerates the optimization process, but also significantly improves the quality of ILT.
[en] A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 x 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.
[en] A 1024 bits fully decoded electrically writable and erasable non volatile ROM is described. Memory cells and peripheral circuits are made using P channel silicon on sapphire enhancement depletion technology
[fr]On decrit une memoire morte non remanente de 1024 bits, entierement decodee, a enregistrement et effacement electrique. Cellules memoire et circuits peripheriques sont fabriques par technologie de canal P silicium/saphir a enrichissement/appauvrissement
[en] Hardened dielectrically isolated integrated circuits are being developed to provide an order of magnitude improvement in radiation response over previous bipolar technology. This study describes (a) the analytical and experimental techniques used to develop the hardened parts, and (b) comparative analytical and test results obtained thus far in the program. This study describes how (a) various element models were defined for CAD usage, (b) how design tolerances were established for the element models, (c) how circuit design margins were established, (d) experimental techniques and equipment used to validate early designs, and (e) comparative analytical and test results
[en] A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to VT1nT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5-μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/0C is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42 μA. (semiconductor integrated circuits)
[en] Plasma etching as applied to many of the materials encountered in the fabrication of LSI's is complicated by loading effect-the dependence of etch rate on the integrated surface area to be etched. This problem is alleviated by appropriate choice of etchant and etching conditions. Appropriate choice of system parameters, generally most concerned with the inherent lifetime of etchant species, may also result in improvement of etch rate uniformity on a wafer-by-wafer basis