[en] A memory is a physical system for transferring information form one moment in time to another, where that information concerns something external to the system itself. This paper argues on information-theoretic and statistical mechanical grounds that useful memories must be of one of two types, exemplified by memory in abstract computer programs and by memory in photographs. Photograph-type memories work by exploring a collapse of state space flow to an attractor state. (This attractor state is the open-quotes initializedclose quotes state of the memory.) The central assumption of the theory of reversible computation tells us that in any such collapsing, regardless of whether the collapsing must increase in entropy of the system. In concert with the second law, this establishes the logical necessity of the empirical observation that photograph-type memories are temporally asymmetric (they can tell us about the past but not about the future). Under the assumption that human memory is a photograph-type memory, this result also explains why we humans can remember only our past and not our future. In contrast to photo-graph-type memories, computer-type memories do not require any initialization, and therefore are not directly affected by the second law. As a result, computer memories can be of the future as easily as of the past, even if the program running on the computer is logically irreversible. This is entirely in accord with the well-known temporal reversibility of the process of computation. This paper ends by arguing that the asymmetry of the psychological arrow of time is a direct consequence of the asymmetry of human memory. With the rest of this paper, this explains, explicitly and rigorously, why the psychological and thermodynamic arrows of time are correlated with one another. 24 refs

[en] A novel drain-junction-assisted hot electron programming scheme has been proposed for Si nanocrystal memory devices. Different from the conventional channel hot electron (CHE) injection, two electron injection paths are responsible for the proposed scheme. Experimental results show that the new scheme has a nearly 1 V memory window increase and almost 300 times faster programming speed rather than the conventional CHE method. Meanwhile, improved data retention and endurance characteristics have also been achieved with the enlarged memory window, which is mainly due to less tunnel oxide degradation during the program/erase cycling. Therefore, the new scheme is shown to be more promising for Si nanocrystal memory application

[en] A 1024 bits fully decoded electrically writable and erasable non volatile ROM is described. Memory cells and peripheral circuits are made using P channel silicon on sapphire enhancement depletion technology

No abstract available

[en] We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

[en] In this study, the wafer warpage resulting from common source line tungsten (CSL W) is investigated in 3D NAND flash memory. It is found that the warpage is related to the annealing conditions after CSL W deposition, and it reduces exponentially with increasing annealing temperature or linearly with increasing annealing time. This result shows that the effect of annealing temperature on warpage is greater than that of time. Consequently, spike annealing with a low thermal budget is proposed to achieve the desired reduction of warpage as long as the annealing temperature is adequate. This work provides an effective approach to solve the wafer warpage problem in 3D NAND flash memory manufacturing. (letter)

[en] A quantitative comparison between zone memories, pseudorandom addressed memories and an alternative special purpose memory (spread zone memory) in which the distance between any two transformed descriptors, at first adjacent, is independent of the descriptors pair and results the maximum one is presented. This memory has not been particularly considered at present in spite of its efficiency and its simple implementation

[en] This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC. (semiconductor integrated circuits)

[en] After some 20 years of valiant service providing the mainstay computing services, machines based on a mainframe architecture are beginning to show signs of age. With the advent of personal computers, less expensive hardware and increased networking, mainframe systems providing a range of services for hundreds, even thousands, of users are being discarded in favour of distributed computing solutions. During these twenty years, the traditional mainframe provided the inherent integration or 'glue' for major computing environments. This was particularly the case with high energy physics laboratories, handling enormous quantities of data. At CERN, the VM system (CERNVM) was, and still is, an integral part of CERN's day-to-day working environment, with some 15,000 tape mounts per week and a thousand logged-on users at peak periods

[en] Multilevel-cell (MLC) phase change memory (PCM) usually evaluated in the program method, delay or write energy while the endurance characteristic has not been focused on. In this paper, we exploit a staircase-up program and verify method in the current-driven 4 Mb PCM chip to achieve MLC storage. The direct results of the change in the R–I characteristic and resistance distribution during the cycles are displayed. According to the measurement, the PCM device shows four separable resistance levels after 10⁶ operation cycles with a decreasing resistance of full-crystalline state. And the resistance drift and read disturb which affect the cell reliability also are briefly tested. The MLC device shows a good performance where four resistance levels can be separated well after 1000 s and the read endurance under 0.3 V is retained up to 10⁹ cycles. (paper)