[en] Detectors for colliding beam experiments at RHIC will provide 4pi coverage and are expected to contain from 10**5 to 10**6 channels. As the 2 to 5usec required to generate first-level triggers is long compared with RHIC's 114nsec beam crossing interval, there will be a need not only to deal with signals from a great number of channels but also to store and tag these signals over many beam crossings. The authors are concentrating their efforts on developing the switched-capacitor (SC) analog memory as the generic mechanism for storing detector signals. Switched-capacitor circuits can be implemented using metaloxide-semiconductor (MOS) technology; and, for development work, they have relatively easy access to a number of foundries running different MOS processes the choice of which would depend on the exact nature of their application. In terms of memory applications, several MOS-based designs have been reported in the literature. MOS technology is generally considered to have advantages over charge-coupled devices in terms of lower power dissipation, lower noise, better linearity, better radiation hardness, and lower cost: all desirable characteristics for a device to be used in a particle detector. However, the authors have recently learned of new developments in CCD technology at MIT's Lincoln Laboratory, and they find that the advantage of MOS technology over CCD technology, at least in terms of the parameters mentioned above, may not be as marked as once thought. Since CCD's have some interesting features which make them potentially useful for pipeline trigger applications, if not for the more general storage applications they are considering here, they intend to keep in close contact with this work