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[en] A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy
Journal
Nuclear Physics. B, Proceedings Supplements; ISSN 0920-5632; 
; CODEN NPBSE7; v. 106-107(1-3); p. 177-183
; CODEN NPBSE7; v. 106-107(1-3); p. 177-183