[en] The authors present the SEU (single event upset) sensitivity of 31 SRAM (static random access memory) and 8 DRAM (dynamic random access memory) according to their technologies. 2 methods have been used to compute the SEU rate: the NCS (neutron cross section) method and the BGR (burst generation rate) method, the physics data required by both methods have been either found in scientific literature or directly measured. The use of new technologies implies a quicker time response through a dramatic reduction of chip size and of the amount of energy representing 1 bit. The reduction of size makes less particles are likely to interact with the chip but the reduction of the critical charge implies that these interactions are more likely to damage the chip. The SEU sensitivity is then parted between these 2 opposed trends. Results show that for technologies beyond 0,18 μm these 2 trends balance roughly. Nevertheless the feedback experience shows that the number of errors is increasing. This is due to the fact that avionics requires more and more memory to perform numerical functions, the number of bits is increasing so is the risk of errors. As far as SEU is concerned, RAM devices are less and less sensitive comparatively for 1 bit, and DRAM seem to be less sensitive than SRAM. (A.C.)