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[en] Future hybrid pixel detectors require smaller pixels in order to improve single point resolution and to deal with an increasing hit rate. Technology shrinking is the approach followed by the industry since decades, but starts presenting some disadvantages in term of performances and cost at very small feature size. New 3D integration technologies offer an alternative to feature reduction while bringing new benefits. In the framework of the upgrade of ATLAS pixel detector, a 3D version of the readout chip is investigated. Splitting the pixel functionalities into two separate levels will reduce pixel size and opens the opportunity to take benefit of technology mixing. Based on a previous prototype of the readout chip FE-I4, the design of a hybrid pixel readout chip using three-dimensional technology is pursued in a collaboration between Bonn (Germany), CPPM (France) and LBNL (USA). In order to disentangle effects due to the translation to the new 130 nm technology from effects due to the 3D architecture itself, a first 2D translation of FE-I4 prototype has also been done. The focus of the presentation will be the 3D designs developed, the issues encountered and the development of test system for 3D prototypes.