[en] A major upgrade of the KEKB factory (Tsukuba, Japan) is foreseen until 2013, aiming at a luminosity of up to 8x10³⁵cm^-2s^-1, which is about 40 times the present value. Accordingly, a similar increase is expected for trigger rate and occupancy of the Silicon Vertex Detector (SVD). The current readout system has a shaping time of 800 ns, no multi-event memory and thus requires a trigger within this period. As it already operates at its limit, it obviously has to be replaced for the upgrade. We developed a readout system using the APV25 chip with a shaping time of 50 ns and an integrated analog pipeline. By taking six consecutive samples of the shaper output and processing these data with FPGAs on a VME module we can determine timing information of the hits with a precision of about 3 ns RMS, which enables occupancy reduction and thus eases subsequent track finding. Thanks to reading several samples the system can tolerate a trigger jitter of up to ±2 clocks. A dedicated pipelined data processor is implemented for each input, which encodes position, pulse height and time information of a hit in a single 32 bit word. The acceptable trigger rate is limited by the time needed to read out six samples from the APV25.