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Krivda, M.; Ban, J.; Burns, M.; Caselle, M.; Kluge, A.; Manzari, V.; Torcato de Matos, C.; Morel, M.; Riedler, P.; Aglieri Rinella, G.; Sandor, L.; Stefanini, G., E-mail: Marian.Krivda@cern.ch2010
AbstractAbstract
[en] The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracking system (ALICE Collaboration, 1999) . The SPD is built with 120 detector modules (half-staves) and contains about 10 million pixels in total. The half-staves are connected to the off-detector electronics, housed in a control room 100 m away, via bidirectional optical links. The stream of data from the front-end electronics is processed in 20 VME readout modules, called routers, based on FPGAs. Three 2-channel link-receiver daughter cards, also based on FPGAs, are plugged in each router. Each link-receiver card receives data via the optical link from two half-staves, applies the zero suppression and passes them to the router to be processed and sent to the ALICE-DAQ system through the detector data link (DDL). The SPD control, configuration and data monitoring are performed using the VME interface embedded in the router.
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Source
11. Pisa meeting on advanced detectors; La Biodola, Elba (Italy); 24-30 May 2009; S0168-9002(09)01952-4; Available from http://dx.doi.org/10.1016/j.nima.2009.10.047; Copyright (c) 2009 Elsevier Science B.V., Amsterdam, The Netherlands, All rights reserved.; Country of input: International Atomic Energy Agency (IAEA)
Record Type
Journal Article
Literature Type
Conference
Journal
Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment; ISSN 0168-9002;
; CODEN NIMAER; v. 617(1-3); p. 549-551

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