[en] A deterministic bunch to bucket transfer system is currently under development in the frame of the FAIR project at GSI. To achieve our accuracy requirements, a set of hardware modules will be implemented. These hardware modules are expected to provide values such as the relative phase advance between the RF systems of both, the source and the target synchrotron according to an external timing system. These values are exchanged via optical fibers between different supply rooms, and the considered RF signals are re-synthesized locally. These re-synthesized signals are synchronized to enable a precise phase advance control between the synchrotrons' RF systems. The first step of the development consists in modeling the actual DDS and DSP-based LLRF environment of the SIS18 under Ptolemy-II. We expect to use this simulation to refine our timing expectations regarding the synchronization process and the inter-module communication protocols and design the synchronization function, which will be implemented on the hardware modules.