[en] It has long been believed that carrier mobilities in semiconductors can be calculated by Fermi s golden rule (Born approximation). Phenomenological models for scattering amplitudes are typically used for engineering- level device modeling. Here we introduce a parameter-free, first-principles approach based on complex- wavevector energy bands that does not invoke the Born approximation. We show that phonon-limited mobility is controlled by low-resistivity percolation paths and that in ionized-impurity scattering one must account for the effect of the screening charge, which cancels most of the Coulomb tail.Finally, calculated electron mobilities in silicon are in agreement with experimental data.

[en] In this work, the self-heating effect (SHE) on metal gate multiple-fin SOI FinFETs is studied by adopting the ac conductance technique to extract the thermal resistance and temperature rise in both n-channel and p-channel SOI FinFETs with various geometry parameters. It is shown that the SHE degrades by over 10% of the saturation output current in the n-channel and by over 7% in the p-channel. The extracted thermal resistances R_th increase with the scaled down gate length, reducing the number of fin and shrinking the fin width. The temperature rise caused by the SHE increases with the scaled down gate length, increasing the number of fin and shrinking the fin width under the saturated operation condition. Additionally, due to a larger power density in the n-channel SOI FinFETs under the same bias condition, the temperature in the n-channel FinFETs is higher than that in the p-channel FinFETs. Because the Si thermal conductivity decreases as the temperature increases, R_th is larger in the n-channel FinFETs than in the p-channel FinFETs. Therefore, tradeoffs have to be made between the thermal properties and the device’s electrical performance by careful design optimizations of SOI FinFETs. (paper)

[en] Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3–30× contrast), the operation of large (> 1000×1000 device) arrays at low power tends to require quite large (> 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line—which would eliminate any opportunity for 3D stacking—has been difficult. We review our work at IBM Research—Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1–7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (>1e7), a significant voltage margin V_m (over which current <10 nA), and ultra-low leakage (< 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions < 30 nm and thicknesses < 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on Cu⁺ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (< 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V. (invited review)

[en] One of the outstanding features of memristors is their principle possibility to store more than one binary value in a single memory cell. Due to their further benefits of non-volatility, fast access times, low energy consumption, compactness and compatibility with CMOS logic, memristors are excellent devices for storing register values nearby arithmetic units. In particular, the capability to store multi-bit values allows one to realise procedures for high-speed arithmetic circuits, which are not based on usual binary but on ternary values. Arithmetic units based on three-state number representation allow carrying out an addition in two steps, i.e., in O(1), independent of the operands word length n. They have been well-known in literature for a long time but have not been brought into practice because of the lack of appropriate devices to store more than two states in one elementary register or main memory cell. The disadvantage of this number representation is that a corresponding arithmetic unit would require a doubling of the memory capacity. Using memristors for the registers can avoid this drawback. Therefore, this paper presents a conceptual solution for a three-state adder based on tri-stable memristive devices. The principal feasibility of such a unit is demonstrated by SPICE simulations and the performance increase is evaluated in comparison with a ripple-carry and a carry-look-ahead adder. (paper)

[en] Near-field scanning optical microscopy (NSOM) is applied for analyzing GaN-based diode lasers. The measurements are carried out at the front facets of standard devices without any additional preparation. Four different schemes for luminescence and photocurrent detection are applied. The results allow for a detailed analysis of the epitaxial layer sequence, the waveguide mode, the impact of defect absorption, and efficiencies of carrier transfer into the quantum well. Moreover, the effective potential profile as formed by both layer structure and doping profile is imaged. Features being spatially separated by only 30 nm are safely resolved. Our results pave the way towards non-destructive nanoscopic analysis of wide-bandgap optoelectronic devices. (fast track communication)

[en] We present the results from distributed feedback (DFB) lasers with emission wavelengths ranging from 760 to 810 nm and focus on the optimization of Bragg gratings realized with a patterned GaAsP layer that is overgrown with an AlGaAs cladding layer. The impact of the thickness and material composition of the GaAsP grating lines on the DFB laser performance is theoretically and experimentally investigated. 767 nm ridge waveguide DFB lasers with optimized gratings show excellent optoelectronic characteristics in terms of slope efficiency (0.9 W A⁻¹) and linewidth (11 kHz). (paper)

[en] Laminated thin films of lithium-ion-exchanged montmorillonite nanosheets were prepared, and their anisotropy in lithium ion conduction was investigated. For the films with 0.70 µm thickness, the lithium ion conductivities at 30 °C in the directions parallel and perpendicular to the film plane (σ_//, σ_⊥) were determined by alternative current impedance measurements and found to be 4.3 × 10⁻² and 5.7 × 10⁻⁶ S cm⁻¹, respectively. The dependence of σ_⊥ on the nanosheet size for the films composed of nanosheets with different lateral sizes was also investigated. σ_⊥ decreased as the lateral size of the nanosheets increased. A model for the lithium ion conduction path in the nanosheet-laminated films is proposed, and the dependence of conduction on the nanosheet size is discussed. (paper)

[en] The interest in GaN for logic applications is increasing. With complementary logic architectures requiring the lowest power consumption, the need for GaN-based p-channel transistors is growing. Yet, the knowledge and the maturity of p-channel devices is far behind those of their n-channel counterparts. By analysing p-channel transistors with a high on/off ratio and a low subthreshold swing under elevated temperatures, we attempt to improve this situation. This is the first report on transistor operation at temperatures as high as 175 °C. (paper)

[en] Wet etching of InAl(Ga)N/GaN structures has been studied in detail by means of Rutherford backscattering spectroscopy, x-ray diffraction, atomic force microscopy and capacitance–voltage profiling (C–V). The samples used for the study were grown on three different substrates (sapphire, silicon carbide and silicon(111)). Nearly lattice-matched compositions were measured for all the samples. We obtained different etching rate depending on the homogeneity and root-mean-square roughness of the surface as well as the underlying substrate, attributing the difference possibly to the presence of threading dislocation in the sample. The study interest is correlated to the possibility to control at a very precise level the thickness etching of the material, making it possible to fabricate normally-off recessed gate high-electron-mobility-transistors. (paper)

[en] We report the investigation of boron ion implantation as a device field isolation process for GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure. In the mesa isolation region of a bar-type MOSFET, a parasitic MOS-channel existed and widened the designed channel width, which would result in an overestimated mobility compared with a ring-type MOSFET. After boron ions implantation in the isolation region, the overestimation of field-effect mobility of bar-type MOSFETs was eliminated. The sub-threshold characteristics and on-state drain current of the bar-type MOSFETs coincide with the ring-type devices. Long-channel ring-type MOSFETs, with and without ion implantation, were fabricated on the recess region to evaluate the sub-threshold characteristics. The MOSFETs with boron ions implanted into the recess region showed a low drain current up to the gate bias of 10V. The result indicated that boron ion implantation prevented the formation of parasitic MOS-channel in the isolation region and achieved field isolation. The current–voltage characteristics of MOSFETs with the normal recess condition demonstrated no degradation of device performance after boron ions implanted into the isolation region. Boron ion implantation by further optimization can be a field isolation method for GaN MOSFETs. (paper)