[en] It has long been believed that carrier mobilities in semiconductors can be calculated by Fermi s golden rule (Born approximation). Phenomenological models for scattering amplitudes are typically used for engineering- level device modeling. Here we introduce a parameter-free, first-principles approach based on complex- wavevector energy bands that does not invoke the Born approximation. We show that phonon-limited mobility is controlled by low-resistivity percolation paths and that in ionized-impurity scattering one must account for the effect of the screening charge, which cancels most of the Coulomb tail.Finally, calculated electron mobilities in silicon are in agreement with experimental data.

[en] In this work the investigations of the argon inductively coupled plasma sputtering of the Pb_1−xSn _xTe thin films with the composition variation of x = 0.16–0.95 grown by hot wall deposition technique on glass substrates were carried out. As-grown films had a columnar polycrystalline structure with the grain lateral dimensions of 0.2–5.0 μm, and the dependence of the lattice constant on composition x had a linear behaviour described by the Vegard’s law. Energy dispersive x-ray microanalysis showed the presence of 5–8 at.% of oxygen in the films, which can be accumulated from the ambient air or from the substrate in the inter-grain boundaries. A phenomenon of a sputtering rate decrease for the polycrystalline lead tin telluride films in comparison to the single-crystal films is discussed. A novel important phenomenon of the formation of nanostructure arrays on the surface of the Pb_1−xSn _xTe thin films with the dependence on the sputtering rate during plasma treatment is reported. (papers)

[en] Doping of BiOCuSe at the copper site with divalent cadmium and zinc cations has been investigated. Analysis of the powder x-ray diffraction data indicates that the ZrCuSiAs structure of BiOCuSe is retained up to substitution levels of 10 and 5 at.% for Cd²⁺ and Zn²⁺, respectively. Substitution of monovalent Cu⁺ with divalent Cd²⁺ or Zn²⁺ leads to an increase in the magnitude of the electrical resistivity and the Seebeck coefficient. All synthesized materials behave as p-type semiconductors. (paper)

[en] This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio. (paper)

[en] Engineered or ‘virtual’ substrates are of interest to extend the range of epitaxially-grown semiconductor heterostructures available for device applications. To this end, elastically strain-relaxed square features up to 30 µm in size and having an in-plane lattice constant as much as 0.49% larger than the lattice constant of GaAs were fabricated from MOCVD-grown GaAs/In_0.08Ga_0.92As/GaAs heterostructures by the in-place bonding method, using either AlAs or Al_0.7Ga_0.3As as the sacrificial layer. TEM images show that the solution-bonded interface is flat with a network of sessile edge dislocations that accommodates the different in-plane lattice constants of the feature and the GaAs substrate and a small rotation of the bonded features. Micro-Raman spectroscopy, which has a spatial resolution of ∼1 µm, was shown to be useful for characterizing lattice mismatch strain ≥ 0.0023, i.e. with an order of magnitude lower sensitivity than high-resolution XRD. (paper)

[en] In this work, we revisit the requirement of higher channel doping (≥10¹⁹ cm⁻³) in junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (10¹⁸ cm⁻³) ultra low power (ULP) JL transistors perform significantly better than heavily doped (10¹⁹ cm⁻³) devices. JL MOSFETs with moderate doping results in the spreading out of carriers across the entire silicon film instead of being localized at the center of the film. This improves gate controllability leading to higher on–off current ratio and lower intrinsic delay for ULP subthreshold logic applications. Additional benefits of using a channel doping concentration of 10¹⁸ cm⁻³ instead of conventional heavily doped design is the significant reduction in threshold voltage sensitivity values (by ∼70–90%) with respect to film thickness and gate oxide thickness. Further improvement in ULP performance metrics can be achieved by limiting the source/drain implantation away from the gate edge. This design, specifically for ULP, allows the requirement of gate workfunction to be reduced from p⁺-poly (∼ 5.1 eV) to near about midgap values (∼ 4.8 eV). On–off current ratio and intrinsic delay for optimized JL devices are compared for low standby power projections of the technological roadmap. A 6T-SRAM cell operating at 0.8 V with 25 nm JL devices exhibits a static noise margin of 151 mV with gate workfunction offset of 0.2 eV with respect to midgap value (4.72 eV). The results highlight new viewpoints for realizing improved low power JL transistors. (paper)

[en] Anatase TiO₂ nanorod arrays (NRAs) are difficult to grow on transparent conductive fluorine-doped tin oxide (FTO) substrates via hydrothermal synthesis. Published hydrothermal products are either rutile NRAs or anatase nanorods dispersions. In this study, single-crystalline anatase NRAs have been grown on FTO by hydrothermal synthesis in tetramethylammonium solution (TMAOH). The introduction of anatase seed layer on FTO before growth plays a key role. Experimental parameters such as growth time, reaction temperature and reactant concentration were investigated to control the morphology of the nanorods. X-ray diffraction reveals that the prepared nanorods are well crystallized anatase. The enhanced (0 0 4) peak in XRD patterns and SEM images indicates the nanorods grow vertically aligned on FTO. HRTEM and SAED patterns confirm that a single nanorod is approximately 50 nm in diameter and is single-crystalline. A growth mechanism controlled by a seed decomposition-growth process has been proposed. Furthermore, photocatalytic properties and dye-sensitized solar cells performances of the synthesized NRAs were measured. Variations in cell-performances resulting from varying the thickness of anatase NRAs were studied. The power conversion efficiency (PCE) of prepared anatase NRAs photoanode is higher than that of the P25 photoanode with the similar thickness. A PCE of 2.1% was obtained with only 2.25 µm thick NRAs. (paper)

[en] This paper presents the low-temperature characteristics of flat-band (V_FB) and low-field mobility in accumulation regime (µ_0acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate V_FB. Additionally, the gate oxide capacitance per unit area C_ox and the doping concentration N_D were evaluated as well. Accounting for the position of V_FB and the charge based analytical model of JLTs, bulk mobility (µ_B) and µ_0acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µ_B and µ_0acc with gate length in planar and tri-gate nanowire JLTs. (paper)

[en] A 3D drift-diffusion device simulation tool with quantum corrections has been applied to study the off-current, threshold voltage and sub-threshold slope variability induced by the metal gate granularity using a Voronoi approach, and line edge roughness using Fourier synthesis, in a 25 nm Si FinFET. The discretization based on the finite element method allows for an accurate description of the 3D geometry. We have simulated 4000 variations of the device to study the metal gate granularity using four different metal grain sizes. The results for the threshold voltage variability ranged from 8.6 mV, for a 3 nm grain size, to 25.9 mV, for a 10 nm grain size. The effect of the grain size was studied and we found an inverse square root dependence of the variability for the three figures of merit. The mean threshold voltage and sub-threshold slope have monotonous decrease with the decrease in metal grain size suggesting that the device power consumption and switching speed can be improved by reducing the grain size. The corresponding threshold voltage variability can reach up to 8.2 mV when RMS = 3 nm and the correlation length is 50 nm. (paper)

[en] A simple and reliable method to determine the junction temperature of GaN-based light-emitting diodes (LEDs) is presented in this paper. The variation of resistance of doped GaN with temperature is advantageously used to measure junction temperature. A simple calibration relating to temperature and resistance is measured and shows excellent agreement with the model analysis. The junction temperature of the pulsed-driving LEDs is measured by resistance meter and shows good agreement with that by the forward voltage method. Experimental results obtained by the described method are presented and discussed. The temperature-dependent resistance method has potential to be a very useful alternative for measurement of temperature in electronic and optoelectronic devices. (paper)