[en] A reconfigurable multi-mode direct-conversion transmitter (TX) with integrated frequency synthesizer (FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320–460 MHz and 620–920 MHz. The lowest phase noise can be −107 dBc/Hz at a 100 kHz offset and −126 dBc/Hz at a 1 MHz offset. The transmitter features a + 10.2 dBm peak output power with a +9.5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth. (semiconductor integrated circuits)

[en] A Matlab (2009a) program was developed to simulate the photons emitted by the LED chips. The photons' transmission, reflection, and refraction in phosphor layers with different shapes were calculated in this program. The CCT was calculated at different emergent angles with different layer profiles, such as planar layer, hemispherical layer (with different diameters), half ellipsoid layer and other irregular shapes. As a consequence of optimization of angular color uniformity, the trend of configuration of the phosphor layer was discussed and analyzed. (semiconductor materials)

[en] An OFET charge model, as well as its parameter extraction method are presented. The fitting results are also discussed and different OFET model characters are compared. Some basic OFET based digital circuit blocks, including the inverter, NAND, and ring oscillator are also developed, which would be considered to be helpful to the design of relevant applications. (semiconductor integrated circuits)

[en] Pn junctions based on single crystalline tellurium supersaturated silicon were formed by ion implantation followed by pulsed laser melting (PLM). P type silicon wafers were implanted with 245 keV ¹²⁶Te⁺ to a dose of 2 × 10¹⁵ ions/cm², after a PLM process (248 nm, laser fluence of 0.30 and 0.35 J/cm², 1–5 pulses, duration 30 ns), an n⁺ type single crystalline tellurium supersaturated silicon layer with high carrier density (highest concentration 4.10 × 10¹⁹ cm⁻³, three orders of magnitude larger than the solid solution limit) was formed, it shows high broadband optical absorption from 400 to 2500 nm. Current—voltage measurements were performed on these diodes under dark and one standard sun (AM 1.5), and good rectification characteristics were observed. For present results, the samples with 4–5 pulses PLM are best. (semiconductor materials)

[en] Polarity optimization for mixed polarity Reed—Muller (MPRM) circuits is a combinatorial issue. Based on the study on discrete particle swarm optimization (DPSO) and mixed polarity, the corresponding relation between particle and mixed polarity is established, and the delay-area trade-off of large-scale MPRM circuits is proposed. Firstly, mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO (HDPSO). Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model. Finally, the proposed algorithm is testified by MCNC Benchmarks. Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits. (semiconductor integrated circuits)

[en] Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 10¹⁶ to 5 × 10¹⁹ cm⁻³ of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices. (paper)

[en] This paper presents a high-responsivity and high-speed InGaAs/InP PIN photodetector integrated onto the silicon waveguide substrate utilizing the divinyltetramethyldisiloxane-benzocyclobutene (DVS-BCB) adhesive bonding method. A grating coupler is adopted to couple light from the fiber to the silicon waveguide. Light in the silicon photonic waveguide is evanescently coupled into the photodetector. The integrated photodetector structure is first simulated using the FDTD (finite difference time domain) solutions software and the simulation results show a detection efficiency of 95%. According to the simulation result, the integrated photodetector is fabricated. The measured responsivity of the fabricated integrated photodetector with a detection length of 30 μm is 0.89 A/W excluding the coupling loss between the fiber and the grating coupler and the silicon propagation loss at the wavelength of 1550 nm with a reverse bias voltage of 3 V. Measured 3-dB bandwidth is 27 GHz using the Lightwave Component Analyzer (LCA). The eye diagram signal test results indicate that the photodetector can operate at a high speed of 40 Gbit/s. The integrated photodetector is of great significance in the silicon-based optoelectronic integrated chip which can be applied to the optical communication and the super node data transmission chip of the high-performance computer. (paper)

[en] Advancement in doping other elements, such as Ce, Dy, Ni, Sb, In and Ga in ZnO^[1], have stimulated great interest for high-temperature thermoelectric application. In this work, the effects of Al-doping in a ZnO system on the electronic structure and thermoelectric properties are presented, by experiment and calculation. Nanosized powders of Zn_1−xAl_xO ( x = 0,0.01, 0.02, 0.03 and 0.06) were synthesized by hydrothermal method. From XRD results, all samples contain ZnO as the main phase and ZnAl₂O₄ (spinel phase) peaks were visible when Al additive concentrations were just 6 at%. The shape of the samples changed and the particle size decreased with increasing Al concentration. Seebeck coefficients, on the other hand, did not vary significantly. They were negative and the absolute values increased with temperature. However, the electrical resistivity decreased significantly for higher Al content. The electronic structure calculations were carried out using the open-source software package ABINIT^[2], which is based on DFT. The energy band gap, density of states of Al-doped ZnO were investigated using PAW pseudopotential method within the LDA + U . The calculated density of states was then used in combination with the Boltzmann transport equation^[3] to calculate the thermoelectric parameters of Al-doped ZnO. The electronic band structures showed that the position of the Fermi level of the doped sample was shifted upwards in comparison to the undoped one. After doping Al in ZnO, the energy band gap was decreased, Seebeck coefficient and electrical conductivity were increased. Finally, the calculated results were compared with the experimental results. The good agreement of thermoelectric properties between the calculation and the experimental results were obtained. (paper)

[en] A novel high-order curvature compensation negative voltage bandgap reference (NBGR) based on a novel multilevel compensation technique is introduced. Employing an exponential curvature compensation (ECC) term with many high order terms in itself, in a lower temperature range (TR) and a multilevel curvature compensation (MLCC) term in a higher TR, a flattened and better effect of curvature compensation over the TR of 165 °C (−40 to 125 °C) is realised. The MLCC circuit adds two convex curves by using two sub-threshold operated NMOS. The proposed NBGR implemented in the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm BCD technology demonstrates an accurate voltage of −1.183 V with a temperature coefficient (TC) as low as 2.45 ppm/°C over the TR of 165 °C at a −5.0 V power supply; the line regulation is 3 mV/V from a −5 to −2 V supply voltage. The active area of the presented NBGR is 370 × 180 μm². (paper)

[en] A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic. (paper)