No abstract available

No abstract available

[en] Our group at Ecole Polytechnique has constructed and used bit slice processors since 1976. Our first generation processor, named μ 77, has been used at C.E.R.N. on a PS experiment from 1977 to 1979. The first results of this S 157 experiment are published in Phys. Lett., B v. 94(1980). Our second generation processor called CAB (CAMAC Booster) has been used in 1980 for a follow-up experiment S 157b, also at C.E.R.N. PS. During the last year more than 15 CABs have been built, and are used in different applications. Therefore we have a relatively long experience of using a bit slice processor in a high energy physics experiment. We shall focus this paper on the specific aspects of this experience, namely the 'on-line physics' at S 157 experiment and the 'CAMAC boosting' concept, after an abrigded technical presentation of our CAB processor. (orig.)

[en] In the first part of this paper the history of the 168/E work at CERN is reviewed, this is followed by a short description of the hardware and software in use and finally some examples of future applications are given. In the second part of the paper the limitations of the present 168/E design are discussed and the ways that a new design, Mark 2, could overcome them are presented. (orig.)

[en] This paper describes the design of a bit-slice based computer, which has been developed for use in data acquisition and control applications. The main design goals have been to provide fast response to external events, and sufficient processing capability to perform data reduction in real time. The initial application of this computer has been in airborne, geophysical surveying, where such instruments as Gamma-ray spectrometers, magnetometers and navigation equipment are involved. In order to meet the response requirement mentioned above, a microinterrupt facility has been incorporated. Microinterrupts are serviced in microcodes routines which can be initiated within a maximum of two microinstruction cycle times from an external event. This facility makes it possible to implement powerful input/output control functions without the need for complex and specialized hardware interfaces for each instrument. (orig.)

[en] The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

[en] Over the past 3 years, CAVIAR (CAMAC Video Autonomous Read-out) microcomputers have been applied in growing numbers at CERN and related institutes. As typical user programs expanded in size, and the incorporated firmware libraries were enlarged also, the microprocessor addressing limit of 64 Kbytes became a serious constraint. An enhanced microcomputer, SUPER CAVIAR, has now been created by the incorporation of memory mapping to expand the physical address space to 344 Kbytes. The new facility provides independent firmware and RAM maps, dynamic allocation of common RAM, automatic inter-page transfer modes, and a RAM/EPROM overlay. A memory-based file system has been implemented, and control and data can be interchanged between separate programs in different RAM maps. 84 Kbytes of EPROM are incorporated on the mapper card itself, as well as an ADLC serial data link. In addition to providing more space for consolidated user programs and data, SUPER CAVIAR has allowed the introduction of several improvements to the BAMBI interpreter and extensions to the CAVIAR libraries. A context editor and enhanced debug monitor have been added, as well as new data types and extended array-handling and graphics routines, including isoline plotting, line-fitting and FFT operations. A SUPER CAVIAR converter has been developed which allows a standard CAVIAR to be upgraded to incorporate the new facilities without loss of the existing investment. (orig.)

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[en] The use of small processors in the experimental program at Brookhaven will be reviewed. FASTBUS, a new data acquisition system, as developed at BNL will also be reviewed. New directions that are planned in these areas will be discussed. (orig.)

No abstract available